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ordering number : en * 5966 d1898rm (ot) no. 5966-1/24 overview the LC74793/jm is a cmos ic that provides pds, vps, and udt data acquisition functions. the LC74793/jm supports microprocessor control of its operating modes and microprocessor read out of data acquired in any of its operating modes. features vps data acquisition (5 or 11 to 15 bytes) vps: video program system pdc (8/30/2) data acquisition (13 to 25 bytes) pdc: program delivery control udt (8/30/1) data acquisition (13 to 25 bytes) udt: unified date and time header (x/00) data acquisition (14 to 45 bytes) status display (8/30/1, 8/30/2) data acquisition (26 to 45 bytes) automatic vps/pdc discrimination mode built-in afc and sync separator circuits synchronization discrimination circuit ? 2 c bus support package dimensions unit: mm 3067-dip24s unit: mm 3112-mfp24s preliminary sanyo: dip24s [LC74793] sanyo: mfp24s [LC74793jm] LC74793, 74793jm sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan vps / pdc slicer ic cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
pin assignment no. 5966- 2 /24 LC74793, 74793jm
no. 5966- 3 /24 LC74793, 74793jm pin functions pin no. pin function description 1 v ss 1 ground digital system ground 2 xtalin crystal oscillator connections connections for the crystal element and capacitors that form the crystal oscillator. also 3 xtalout used for external clock input (fsc, 2fsc, or 4fsc). 4 ctrl1 crystal element switching switches between external clock input mode and crystal oscillator mode. set this pin low for crystal oscillator, and high for external clock input. 5 nc data i/o pdc/vps data i/o. 6 sda i 2 c bus i 2 c bus write address: 01111100 i 2 c bus read address: 01111101 7 scl clock input pdc/vps data clock input. i 2 c bus i 2 c bus external synchronizing signal presence/absence discrimination status output. 8 sync jdg external synchronizing signal a high level is output when synchronizing signals are present. discrimination output this pin outputs the crystal oscillator clock when the rst pin is low. (this reset state output can be disabled with command input.) 9 hout horizontal synchronizing signal output horizontal synchronizing signal output 10 vss2 ground ground. (vco circuit ground) 11 cp out charge pump output charge pump output. connect a low-pass filter to this pin. 12 vco in oscillator control voltage input vco oscillation control voltage input 13 vcor oscillator range adjustment vco oscillation range adjustment resistor connection 14 dav data acquisition output outputs a low level when pdc/vps data has been discriminated 15 v dd 2 power supply (+5 v) power supply (+5 v) (vco system power supply) 16 synin sync separator circuit input internal sync separator circuit video signal input 17 sepc slice level output slice level verification 18 sep out composite synchronizing signal output internal sync separator circuit composite synchronizing signal output inputs the vertical synchronizing signal by integrating the sep out pin output signal. 19 sep in vertical synchronizing signal input applications must connect the sep out pin to this pin through an integration circuit. if unused, connect this pin to vdd1. (this pin is enabled when ctrl2 is high.) vertical synchronizing signal output 20 vout vertical synchronizing signal output this pin outputs the vco clock when the rst pin is low. (this reset state output can be disabled with command input.) controls whether or not the vsync vertical synchronizing signal is input to the sepin 21 ctrl2 sepin input control input. when low: the vsync signal is not input. (the internal vertical separation circuit is used.) when high: the vsync signal is input. 22 cdlr clock phase adjustment connection for the clock phase adjustment resistor. 23 rst reset input system reset input. a pull-up resistor is built in. (this input has hysteresis characteristics.) 24 v dd 1 power supply (+5 v) power supply. (+5 v: digital system power supply)
no. 5966- 4 /24 LC74793, 74793jm parameter symbol conditions ratings unit supply voltage v dd v dd 1 and v dd 2 v ss ?0.3 to v ss + 7.0 v input voltage v in all input pins v ss ?0.3 to v dd 1 + 0.3 v output voltage v out sda, syncjdg, sepout, dav, hout, and vout v ss ?0.3 to v dd 1 + 0.3 v allowable power dissipation pd max ta = 25 c 350 mw operating temperature topr ?0 to +70 c storage temperature tstg ?0 to +125 c specifications absolute maximum ratings parameter symbol conditions ratings unit min typ max supply voltage v dd 1 v dd 1 and v dd 2 4.5 5.0 5.5 v v ih 1 sda and scl 0.8 v dd 1 5.5 v high-level input voltage v ih 2 rst 0.8 v dd 1 v dd 1 + 0.3 v v ih 3 ctrl1 and ctrl2 0.7 v dd 1 v dd 1 + 0.3 v low-level input voltage v il 1 rst, sda, and scl v ss ?0.3 0.2 v dd 1 v v il 2 ctrl1 and ctrl2 v ss ?0.3 0.3 v dd 1 v pull-up resistance rpu rst 25 50 90 k composite video signal input voltage v in 1 synin v dd 1 = 5 v 1.5 2.0 2.25 vp-p input voltage v in 2 xtalin (in external clock input mode) v dd 1 = 5 v 0.10 5.0 vp-p fin = fsc, 2fsc, or 4fsc fosc1 the xtalin and xtalout oscillator pins (4fsc: pal) 17.734 mhz oscillator frequency fosc2 the xtalin and xtalout oscillator pins (2fsc: pal) 8.867 mhz fosc3 the xtalin and xtalout oscillator pins (fsc: pal) 4.433 mhz recommended operating conditions note: note that adequate measure must be taken to prevent noise from entering the xtalin pin when it is used in clock input mod e.
no. 5966- 5 /24 LC74793, 74793jm parameter symbol applicable pins conditions ratings unit min typ max output off leakage current ileak2 sda and dav 1 a high-level output voltage v oh 1 sepout, cpout, syncjdg, v dd 1 = 4.5 v, 3.5 v hout, and vout i oh = ?.0 ma v ol 1 sepout, cpout, syncjdg, v dd 1 = 4.5 v 1.0 v low-level output voltage dav, hout, and vout i ol = 1.0 ma v ol 2 sda v dd 1 = 5.0 v 0.4 v i ol = 3.0 ma i ih rst, sda, scl, ctrl1, ctrl2, v in = v dd 1 1 a input current vcoin i il sda, scl, ctrl1, ctrl2, v in = v ss 1 ? a vcoin with all outputs open operating current drain i dd 1 v dd 1 and v dd 2 and a 17.734 mhz 40 ma crystal electrical characteristics at ta = ?0 to +70 c, v dd 1 = 5 v unless otherwise specified. parameter symbol conditions ratings unit min typ max scl frequency f scl 100 khz bus release time t buf 4.7 s start hold time t hd ; sta 4.0 s scl low-level period t low 4.7 s scl high-level period t hign 4.0 s data hold time t hd ; dat 0 s data setup time t su ; dat 250 ns rise time t r 1000 ns fall time t f 300 ns stop setup time t su ; sto 4.0 s timing characteristics pdc and vps read and write (i 2 c bus timing) at ta = ?0 to +70 c, v dd 1 = 5 0.5 v supplementary documentation ?pdc and vps serial timing (i 2 c bus timing) s: start condition p: stop condition
LC74793/m system block diagram no. 5966- 6 /24 LC74793, 74793jm sync separator and data separator circuit synchronization recognition circuit vertical separator circuit timing generator afc circuit (vco) data acquisition circuit data latch circuit i 2 c interface
control commands the control commands have an 8-bit serial input format. commands consist of a command identification code in the first byte and data in the following bytes. command 0: clock control command command 1: vps/pdc control command 1 command 2: vps/pdc control command 2 command 3: synchronizing signal detection command 1 command 4: synchronizing signal detection command 2 command 5: output control command 1 command 6: output control command 2 command 7: vps/pdc control command 3 command 8: vps/pdc control command 4 command 9: vps/pdc control command 5 command 10: vps/pdc control command 6 once written, the first byte command identification code is retained until the next first byte is written. data is written in second byte only continuous mode. (automatic increment) no. 5966- 7 /24 LC74793, 74793jm display control commands: i 2 c write first byte second byte command command id code data data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command0 (clock control) 1 1 1 1 0 0 0 0 0 fs fs2 fs3 o tst o sys mod rst command1 (vps/pdc control 1) 1 1 1 1 0 0 0 1 0 cpa cpa cpa vpm vpm vpm vpm 2 1 0 3 2 1 0 command2 (vps/pdc control 2) 1 1 1 1 0 0 1 0 0 vmw vmw hbs hbs bms ems dce se2 sel 2 1 command3 (synchronizing signal detection 1) 1 1 1 1 0 0 1 1 0 rn rn rn sn sn sn sn 2 1 0 3 2 1 0 command4 (synchronizing signal detection 2) 1 1 1 1 0 1 0 0 0 0 rne sjn sjn sjn sjc sjc 0 3 2 1 1 0 command5 (output control 1) 1 1 1 1 0 1 0 1 0 sp0 sp0 sp0 sj0 sj0 vnp vsp 2 1 0 1 0 sel sel command6 (output control 2) 1 1 1 1 0 1 1 0 0 0 np1 np0 vi0 hi0 v0t h0t set set kst kst command7 (vps/pdc control 3) 1 1 1 1 0 1 1 1 0 0 ecv ecv ecv ecv ecv ecv 15 14 13 12 11 5 command8 (vps/pdc control 4) 1 1 1 1 1 0 0 0 0 ecp ecp ecp ecp ecp ecp ecp 19 18 17 16 15 14 13 command9 (vps/pdc control 5) 1 1 1 1 1 0 0 1 0 0 ecp ecp ecp ecp ecp ecp 25 24 23 22 21 20 command10 (vps/pdc control 6) 1 1 1 1 1 0 1 0 0 hxa lka msk kmw slh slh slh ll2 slc h1 3 2 1
no. 5966- 8 /24 LC74793, 74793jm command 0 (clock settings command) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 0 identification code. 5 1 clock settings. 4 1 3 0 2 0 1 0 0 0 ?second byte setting for the frequency input to the xtal in pin (pin 2). cdlr can be deleted: the resistor connected to the cdlr pin may be removed. da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 fs 0 1 5 fs2 0 1 4 fs3 0 1 3 0 2 tstmod 0 normal operating mode this bit must be set to 0. 1 test mode 1 0 0 sysrst 0 1 all registers are reset fs fs2 fs3 setting 0 0 0 2fsc 1 0 0 4fsc (cdlr can be deleted) 0 1 1 fsc 0 0 1 2fsc (cdlr can be deleted)
no. 5966- 9 /24 LC74793, 74793jm command 1 (vps/pdc control command 1) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 1 identification code. 5 1 vps/pdc control settings 1. 4 1 3 0 2 0 1 0 0 1 ?second byte data acquisition clock selection. the clock can be shifted relative to the data in units of 8 clock cycles. da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 cpa1 0 1 5 cpa2 0 1 4 cpa0 0 1 3 vpm3 0 1 2 vpm2 0 1 slicer operating mode selection 1 vpm1 0 1 0 vpm0 0 1 cpa2 cpa1 cpa0 clock 0 0 0 no1 0 0 1 no2 0 1 0 no3 0 1 1 no4 1 0 0 no5 1 0 1 no6 1 1 0 no7 1 1 1 no8 m3 m2 m1 mo operating mode 0 0 0 0 vps 0 0 0 1 8/30/2 (pdc) 0 0 1 0 pdc and vps automatic recognition 1 0 0 1 1 8/30/1 (udt) 0 1 0 0 header time 1 0 1 0 1 header time 2 0 1 1 0 header time 3 0 1 1 1 header time 4 1 0 0 0 status display 1 1 0 0 1 status display 2 1 0 1 0 status display 3 1 0 1 1 status display 4 1 1 0 0 pal pulse 1 1 0 1 pdc and vps automatic recognition 2 1 1 1 0 pdc and vps automatic recognition 3 1 1 1 1 pdc and vps automatic recognition 4 note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 10 /24 LC74793, 74793jm command 2 (vps/pdc control command 2) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 2 identification code. 5 1 vps/pdc control settings 2. 4 1 3 0 2 0 1 1 0 0 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 vmwse2 0 from the vertical mask period start return period cpout pin vertical mask period 1 from 10h before the vertical mask period start return period switching 2 5 vmwsel 0 the vertical mask period is the return period cpout pin vertical mask period 1 the vertical mask period is 9h switching 4 hbs2 0 clock run discrimination 1 (2 times) clock run discrimination circuit setting 1 clock run discrimination 2 (4 times) 3 hbs1 0 framing code discrimination 1 framing code discrimination selection 1 framing code discrimination 2 (a single bad bit is ignored) 0 error check enabled (the error check can be turned on or off on 2 bms per-byte basis.) 1 error check disabled (applications can select whether data with errors is held or written for each byte.) 1 ems 0 data hold 1 data write (error bits are set to 0 in vps mode) error check turned on for unused bytes 0 vps: bytes 3, 4, and 6 to 10, pdc: bytes 7 to 12 header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21. 0 dce status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35. error check turned off for unused bytes 1 vps: bytes 3, 4, and 6 to 10, pdc: bytes 7 to 12 header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21. status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35. when set to 0: if there are no errors in bytes for which the error check is turned on, those bytes will be written to p-s (com7-9). when set to 1: data is written to p-s regardless of whether or not errors occurred. when error checking is enabled, specifies the processing when an error occurs in a byte for which error checking was turned off error check setting for unused data bytes biphase (vps), hamming (pdc), odd parity (header) note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 11 /24 LC74793, 74793jm command 3 (synchronizing signal detection command 1) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 3 identification code. 5 1 synchronizing signal detection settings 1. 4 1 3 0 2 0 1 1 0 1 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 rn2 0 1 5 rn1 0 1 4 rn0 0 1 3 sn3 0 1 2 sn2 0 1 1 sn1 0 1 0 sn0 0 1 rn2 rn1 rn0 number of hsync detections 0 0 0 0 (32) 0 0 1 4 (64) 0 1 0 8 (128) 1 0 0 16 (256) external synchronizing signal detection control. signal absent ? present discrimination. sets the sampling period during which sync is continuously detected in the horizontal synchronizing signal period (1h). values in parentheses apply when rne0 (com4) is set to 1. external synchronizing signal detection control. signal present ? absent discrimination. sets the sampling period during which sync cannot be detected consecutively in the horizontal synchronizing signal period (1h). sn3 sn2 sn1 sno number of hsync detections 0 0 0 0 no detection performed 0 0 0 1 32 0 0 1 0 64 0 1 0 0 128 1 0 0 0 256 note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 12 /24 LC74793, 74793jm command 4 (synchronizing signal detection command 2) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 4 identification code. 5 1 synchronizing signal detection settings 2. 4 1 3 0 2 1 1 0 0 0 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 0 5 rne0 0 synchronization signal discrimination absent ? preset: normal values 1 synchronization signal discrimination absent ? preset: values in parentheses 4 sjns3 0 1 3 sjns1 0 1 2 sjns1 0 1 1 sjcs1 0 1 0 sjcs0 0 1 sjns3 sjns2 sjns1 count 0 0 0 none 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 sjcs1 sjcs0 pal ntsc 0 0 677 ns (1/3) 448 ns (1/2) 0 1 903 ns (1/4) 838 ns (1/3) 1 0 450 ns (1/2) 1117 ns (1/4) changes the values used for synchronizing signal discrimination in the absent ? preset direction (com3). setting for the noise exclusion circuit used for synchronizing signal discrimination in the absent ? preset direction. if the number of h signal inputs during a 1h period is greater than or equal to the value listed in the table, the ic determines that the signal is absent. synchronization discrimination. hsyni signal switching clock selection. note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 13 /24 LC74793, 74793jm command 5 (output control command 1) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 5 identification code. 5 1 output control settings 1 4 1 3 0 2 1 1 0 0 1 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 spo2 0 1 5 spo1 0 1 4 spo0 0 1 3 sjo1 0 1 2 sjo0 0 1 1 vnpsel 0 vertical signal falling edge detection 1 vertical signal rising edge detection 0 vspsel 0 vsep: about 8.9 s (ntsc) 1 vsep: about 17.8 s (ntsc) spo2 spo1 spo0 sepout pin 0 0 0 csync 0 0 1 slice data amplitude 0 1 0 o/e 0 1 1 clk (acquisition) 1 0 0 vco 1/1 1 0 1 vco 1/2 1 1 0 vco 1/3 1 1 1 vco 1/4 sjo1 sjo0 syncjdg pin 0 0 syncjdg 0 1 lock 1 0 syncdet 1 1 dxout (sliced data) sepout (pin 18) output switching syncjdg (pin 8) output switching vertical signal acquisition polarity switching. only valid when internal vertical separation used. internal vertical separation time switching note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 14 /24 LC74793, 74793jm command 6 (output control command 2) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 6 identification code. 5 1 output control settings 2. 4 1 3 0 2 1 1 1 0 0 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 0 5 np1 0 pal 1 ntsc 4 np0 0 625 number of scan lines 1 525 3 vioset 0 vsync signal output vout mode setting 1 set up as a general-purpose port 2 hioset 0 hsync signal output hout mode setting 1 set up as a general-purpose port 1 votkst 0 negative polarity (lo) 1 positive polarity (hi) 0 hotkst 0 negative polarity (lo) 1 positive polarity (hi) vout polarity selection. level in parentheses applies when set up as a general-purpose port. hout polarity selection. level in parentheses applies when set up as a general-purpose port. note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 15 /24 LC74793, 74793jm command 7 (vps/pdc control command 3) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 7 identification code. 5 1 vps/pdc control settings 3. 4 1 3 0 2 1 1 1 0 1 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 0 5 ecv15 0 byte 15 biphase error check: on (data retained) 1 byte 15 biphase error check: off (data written) 4 ecv14 0 byte 14 biphase error check: on (data retained) 1 byte 14 biphase error check: off (data written) 3 ecv13 0 byte 13 biphase error check: on (data retained) 1 byte 13 biphase error check: off (data written) 2 ecv12 0 byte 12 biphase error check: on (data retained) 1 byte 12 biphase error check: off (data written) 1 ecv11 0 byte 11 biphase error check: on (data retained) 1 byte 11 biphase error check: off (data written) 0 ecv5 0 byte 5 biphase error check: on (data retained) 1 byte 5 biphase error check: off (data written) vps data specification when bms is 0. items in parentheses are the specification when bms is 1. note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 16 /24 LC74793, 74793jm command 8 (vps/pdc control command 4) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 8 identification code. 5 1 vps/pdc control settings 4. 4 1 3 1 2 0 1 0 0 0 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 0 byte 19 hamming error check on (data retained) 6 ecp19 {bytes 44, 28, 36, 20, 32, 42, 32, 42} 1 byte 19 hamming error check off (data written) {bytes 44, 28, 36, 20, 32, 42, 32, 42} 0 byte 18 hamming error check on (data retained) 5 ecp18 {bytes 43, 27, 35, 19, 31, 41, 31, 41} 1 byte 18 hamming error check off (data written) {bytes 43, 27, 35, 19, 31, 41, 31, 41} 0 byte 17 hamming error check on (data retained) 4 ecp17 {bytes 42, 26, 34, 18, 30, 40, 30, 40} 1 byte 17 hamming error check off (data written) {bytes 42, 26, 34, 18, 30, 40, 30, 40} 0 byte 16 hamming error check on (data retained) 3 ecp16 {bytes 41, 25, 33, 17, 29, 39, 29, 39} 1 byte 16 hamming error check off (data written) {bytes 41, 25, 33, 17, 29, 39, 29, 39} 0 byte 15 hamming error check on (data retained) 2 ecp15 {bytes 40, 24, 32, 16, 28, 38, 28, 38} 1 byte 15 hamming error check off (data written) {bytes 40, 24, 32, 16, 28, 38, 28, 38} 0 byte 14 hamming error check on (data retained) 1 ecp14 {bytes 39, 23, 31, 15, 27, 37, 27, 37} 1 byte 14 hamming error check off (data written) {bytes 39, 23, 31, 15, 27, 37, 27, 37} 0 byte 13 hamming error check on (data retained) 0 ecp13 {bytes 38, 22, 30, 14, 26, 36, 26, 36} 1 byte 13 hamming error check off (data written) {bytes 38, 22, 30, 14, 26, 36, 26, 36} pdc data specification when bms is 0. items in parentheses are the specification when bms is 1. items in curly braces are the bytes for which the odd parity check is turned on or off for headers 1, 2, 3, and 4, and for status 1, 2, 3, and 4. note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 17 /24 LC74793, 74793jm command 9 (vps/pdc control command 5) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command 9 identification code. 5 1 vps/pdc control settings 5. 4 1 3 1 2 0 1 0 0 1 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 0 5 ecp25 0 byte 25 hamming error check on (data retained) 1 byte 25 hamming error check off (data written) 4 ecp24 0 byte 24 hamming error check on (data retained) 1 byte 24 hamming error check off (data written) 3 ecp23 0 byte 23 hamming error check on (data retained) 1 byte 23 hamming error check off (data written) 0 byte 22 hamming error check on (data retained) 2 ecp22 {bytes , , , , 35, 45, 35, 45} 1 byte 22 hamming error check off (data written) {bytes , , , , 35, 45, 35, 45} 0 byte 21 hamming error check on (data retained) 1 ecp21 {bytes , , , , 34, 44, 34, 44} 1 byte 21 hamming error check off (data written) {bytes , , , , 34, 44, 34, 44} 0 byte 20 hamming error check on (data retained) 0 ecp20 {bytes 45, 29, 37, 21, 33, 43, 33, 43} 1 byte 20 hamming error check off (data written) {bytes 45, 29, 37, 21, 33, 43, 33, 43} pdc data specification when bms is 0. items in parentheses are the specification when bms is 1. items in curly braces are the bytes for which the odd parity check is turned on or off for headers 1, 2, 3, and 4, and for status 1, 2, 3, and 4. note: all registers are cleared to 0 when the ic is reset by the rst pin.
no. 5966- 18 /24 LC74793, 74793jm command 10 (vps/pdc control command 6) ?first byte da 0 to 7 register contents notes status function 7 1 first byte identification bit 6 1 command a identification code. 5 1 vps/pdc control settings 6. 4 1 3 1 2 0 1 1 0 0 ?second byte da 0 to 7 register contents notes status function 7 0 second byte identification bit 6 hxall2 0 slice data discrimination time: normal vps/pdc data discrimination period 1 discriminates the vertical return period data in all modes setting 5 lkaslc 0 normal operation 1 always in the locked state 4 mskh1 0 1 afc: a mask is applied to the horizontal signal 3 kmw 0 1 forcibly set to high or low only during the csync period 2 slh3 0 1 1 slh2 0 clock discrimination method switching 1 0 slh1 0 1 mode s321 clock discrimination 0 0 0 0 1 1 1 1 1 1 x x 0 0 0 0 0 0 x x 1 0 0 1 0 0 0 0 0 0 x x 1 1 1 1 1 1 x x 2 0 1 0 1 1 1 1 1 x x x 0 0 0 0 0 x x x 3 0 1 1 0 0 0 0 0 x x x 1 1 1 1 1 x x x 4 1 0 0 x x 1 1 1 1 1 1 0 0 0 0 0 0 x x 5 1 0 1 x x 0 0 0 0 0 0 1 1 1 1 1 1 x x 6 1 1 0 1 1 1 x 0 0 0 x 7 1 1 1 0 0 0 x 1 1 1 x note: all registers are cleared to 0 when the ic is reset by the rst pin.
pdc/vps output data format data is read out in order starting with bit 7 of byte 1. no. 5966- 19 /24 LC74793, 74793jm output data pdc 8/30/mode vps mode header time mode 1 (3) header time mode 2 (4) format1 format2 byte1 bit7 byte15 bit0 byte16 bit0 byte11 bit0 byte38 bit0 byte22 bit0 6 1 1 1 (30) 1 (14) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte17 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 byte2 bit7 byte16 bit0 byte18 bit0 byte12 bit0 byte39 bit0 byte23 bit0 6 1 1 1 (31) 1 (15) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte19 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 byte3 bit7 byte17 bit0 byte20 bit0 byte13 bit0 byte40 bit0 byte24 bit0 6 1 1 1 (32) 1 (16) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte21 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 byte4 bit7 byte18 bit0 byte22 bit0 byte14 bit0 byte41 bit0 byte25 bit0 6 1 1 1 (33) 1 (17) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte23 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 byte5 bit7 byte19 bit0 byte14 bit0 byte5 bit0 byte42 bit0 byte26 bit0 6 1 1 1 (34) 1 (18) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte15 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 byte6 bit7 byte20 bit0 byte24 bit0 byte15 bit0 byte43 bit0 byte27 bit0 6 1 1 1 (35) 1 (19) 1 5 2 2 2 2 2 4 3 3 3 3 3 3 4 byte25 bit0 4 4 4 2 5 1 5 5 5 1 6 2 6 6 6 0 7 3 7 7 7 continued on next page.
no. 5966- 20 /24 LC74793, 74793jm continued from preceding page. output data pdc 8/30/mode vps mode header time mode 1 (3) header time mode 2 (4) format1 format2 byte7 bit7 byte21 bit0 byte13 bit0 1 byte44 bit0 byte28 bit0 6 1 1 1 (36) 1 (20) 1 5 2 2 1 2 2 4 3 3 1 3 3 3 4 1 1 4 4 2 5 1 1 5 5 1 6 1 1 6 6 0 7 1 0 7 7 byte8 bit7 byte13 bit0 error byte16 error byte11 byte45 bit0 byte29 bit0 6 1 information 1 17 information 12 (37) 1 (21) 1 5 2 18 13 2 2 4 3 19 14 3 3 3 4 20 5 4 4 2 5 21 15 5 5 1 6 22 0 6 6 0 7 23 0 7 7 byte9 bit7 byte14 bit0 error byte14 error byte38 (30) error byte22 (14) 6 1 information 2 15 information 39 (31) information 23 (15) 5 2 24 40 (32) 24 (16) 4 3 25 41 (33) 25 (17) 3 4 13 42 (34) 26 (18) 2 5 0 43 (35) 27 (19) 1 6 0 44 (36) 28 (20) 0 7 0 45 (37) 29 (21) byte10 bit7 byte22 bit0 6 1 5 2 4 3 3 4 2 5 1 6 0 7 byte11 bit7 byte23 bit0 6 1 5 2 4 3 3 4 2 5 1 6 0 7 byte12 bit7 byte24 bit0 6 1 5 2 4 3 3 4 2 5 1 6 0 7 byte13 bit7 byte25 bit0 6 1 5 2 4 3 3 4 2 5 1 6 0 7 note: data with the value 1 is output for sections for which there is no output data setting.
no. 5966- 21 /24 LC74793, 74793jm data is read out in order starting with bit 7 of byte 1. status display 1 and 2: 8/30/2 status display 1 and 2: 8/30/1 output data status display mode 1 (3) status display mode 2 (4) pal puls byte1 bit7 byte26 bit0 byte36 bit0 bit0 6 (26) 1 (36) 1 1 5 2 2 2 4 3 3 3 3 4 4 4 2 5 5 5 1 6 6 6 0 7 7 7 byte2 bit7 byte27 bit0 byte37 bit0 bit8 6 (27) 1 (37) 1 9 5 2 2 10 4 3 3 11 3 4 4 12 2 5 5 13 1 6 6 0 0 7 7 0 byte3 bit7 byte28 bit0 byte38 bit0 6 (28) 1 (38) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte4 bit7 byte29 bit0 byte39 bit0 6 (29) 1 (39) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte5 bit7 byte30 bit0 byte40 bit0 6 (30) 1 (40) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte6 bit7 byte31 bit0 byte41 bit0 6 (31) 1 (41) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 continued on next page. note: data with the value 1 is output for sections for which there is no output data setting.
no. 5966- 22 /24 LC74793, 74793jm output data status display mode 1 (3) status display mode 2 (4) pal puls byte7 bit7 byte32 bit0 byte42 bit0 6 (32) 1 (42) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte8 bit7 byte33 bit0 byte43 bit0 6 (33) 1 (43) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte9 bit7 byte34 bit0 byte44 bit0 6 (34) 1 (44) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte10 bit7 byte35 bit0 byte45 bit0 6 (35) 1 (45) 1 5 2 2 4 3 3 3 4 4 2 5 5 1 6 6 0 7 7 byte11 bit7 error byte26 (26) error byte36 (36) 6 information 1 27 (27) information 1 37 (37) 5 28 (28) 38 (38) 4 29 (29) 39 (39) 3 30 (30) 40 (40) 2 31 (31) 41 (41) 1 32 (32) 42 (42) 0 33 (33) 43 (43) byte12 bit7 error byte34 (34) error byte44 (44) 6 information 2 35 (35) information 1 45 (45) 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0 byte13 bit7 6 5 4 3 2 1 0 continued from preceding page. note: data with the value 1 is output for sections for which there is no output data setting.
sample application circuit ?using an external system clock no. 5966- 23 /24 LC74793, 74793jm microcontroller
ps no. 5966- 24 /24 LC74793, 74793jm this catalog provides information as of december, 1998. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ?using a crystal oscillator microcontroller

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